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UNCLASSIFIED 


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REPORT  DOCUMENTATION  PAGE 


Introduction  to  custom  Complementary 
Metal-Oxide  Semiconductor  (CMOS)  Large- 
Scale  Integrated  Circuits  (LSI's)  for 
Digital  Logic  » 


Teclinical  ^emo 


PtMFOMHIHa  OttOAHIZATION  NAMC  AND  ADOAIU 

Harry  Diamond  Laboratories 
2800  Powder  Mill  Road 
Adelphi,  MD  20783 


n.  CONTnOLUNO  OFFICt  NAME  AND  AOOnlM 

Project  Manager  SAM-D 
Redstone  Arsenal,  AL  35809 


lA.  taCURITV  CL  AU.  (ml  Mm  • 


DtATmauTION  STATEMENT  (ml  Mm  HmMrt) 


Approved  for  public  release;  distribution  unlimited. 


IT.  MSrmaUTION  statement  (mi  »m  «AMMCt  mMmW  to  EtocA  SS,  If  «ftonal  Mm  UtM") 


MnMtotFStoMK 


IE.  SUPPLEMEHTARV  NOTES 

HDL  Project:  610568 
DRCMS  Code:  634307.12.17100 


It.  KVf  WOKOKCmmMm  mn  immmnm  mMm  II  mmmmmmmr 

Integrated  circuits 
Digital  logic 
CMOS 
MOS  FET 


AEETNACT  (CmmMmmm  mm  imrmnm  «l<»  M — »»«— if  «■*  IMtoN»  mr  mtrnrnk  m^mrnr) 


This  report  contains  well-Jcnown,  but  seldom  assembled,  infor- 
mation necessary  for  understanding  and  initiating  the  design  of 
complementary  metal-oxide  semiconductor  (CMOS)  large-scale  inte- 
grated circuit  (LSI)  digital  logic  using  arrays  of  gates.  A 
■description  is  given  of  how  CMOS  field-effect  transistors  operate 


un  BOITIOH  OF  I MOVES  IS  I 


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1 SBCUmTV  CLAStlFICATieN  OF  TNIS' 


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SecuWTY  CLASiiiriCATION  OF  THIS  PAOEflWnn  Dmtm  Snl,n4) 


and  how  logic  elements  are  made  using  them.  The  design  of  logic 
circuits  is  given,  including  brief  descriptions  of  Boolean  algebra 
and  Karnaugh  maps.  Finally,  custom  LSI’s  and  the  CMOS  gate  array 
are  briefly  discussed. 


SeCURITY  CLMII^ICATIOH  OY  THIS  HAOEfWh*"  DMm  Enlttd} 


CONTENTS 


Paae 

INTRODUCTION  5 

DEVICE  OPERATION  5 

CIRCUIT  OPERATION  9 

3.1  Inverter 9 

3.2  Transmission  Gate 11 

3.3  Logic  Gates 13 

LOGIC  CIRCUITS 14 

4.1  Memory  Element/Shift  Register  14 

4.2  PresettcUale  D-Type  Flip-Flop 15 

4 . 3 Frequency  Divider  15 

4.4  J-K  Flip-Flop 16 

DERIVING  LOGIC  CIRCUITS  FROM  TRUTH  TABLES 17 

5.1  Truth  Table  17 

5.2  Boolean  Algebra 18 

5.3  Don't  Care  Table 19 

5.4  Karnaugh  Map 20 

5.5  Converting  to  NOR's  and  NAND's 20 

CMOS  LSI  GATE  ARRAY 22 

LITERATURE  CITED  28 

DISTRIBUTION  29 

FIGURES 

1 P-channel  MOS  FET 6 

2 MOS  FET  voltage-current  characteristics  8 

3 CMOS  pair  operation  .....  9 

4 Inverter  voltage-current  characteristics  10 

5 Power  dissipation  11 

6 CMOS  transmission  gate 12 

7 Single-pole  double-throw  or  analog  switch  13 


3 


FIGURES  (Cont'd) 


CMOS  logic  circuits  

Shift  register:  basic  D-type  flip-flop  . . . . 

Presettcible  D-type  flip-flop 

Frequency  divider  stage  

J-K  flip-flop  

J-K  input  truth  table  

Boolean  algebra  

"Don't  Care"  tables  

Karnaugh  map  

DeMorgan's  Theorem  

Evolution  of  J-K  flip-flop  input  logic  circuits 
TCC  051  CMOS  universal  eurray  chip  layout  . . . 

RCA  CMOS  cell  

Two- input  NAND  and  NOR  gates  


1 . INTRODUCTION 

Advemcing  solid-state  electronics  has  now  brought  to  reality 
large-scale  integrated  circuits  (LSI's).  These  integrated  circuits  are 
finding  wide  commercial  use  in  hcuid-held  calculators,  wrist 
watches,^  and  automobile  applications.^  Most  of  these  circuits  are 
custom  LSI's  using  metal-oxide  semiconductor  (MOS)  field-effect 
tremsistors  (FET's).  A conventional  handcrafted  custom  LSI  is  expensive 
to  design  in  the  first  place  and  almost  as  eiq^nsive  to  modify  later. 
An  LSI  has  about  seven  levels  of  masking  with  associated  etchings, 
dopings,  and  diffusions.  Most  chcmges  in  a conventional  custom  LSI 
necessitate  a change  in  all  seven  masks,  therefore  causing  the  high 
expense  for  modifications.  A recent  advance  that  has  signiflcamtly 
lowered  initial  costs  and  modification  costs  is  the  development  of  gate 
arrays , 

One  array  consists  of  1104  transistors  (RCA  TCC  051)  on  a 0,3-in, 
square  silicon  chip.  It  Includes  a number  of  crossover  channels, 
input-output  buffers,  and  protection  circuits.  The  array  is  made  with  a 
fixed  set  of  masks  and,  as  a basic  building  block,  comes  with  a 
metalized  surface.  The  transistors  are  interconnected  by  removing  the 
metal  where  conductors  are  not  required.  Only  one  mask  for  this 
raetalizatlon  pattern  is  made  up  for  each  application,  and  only  one  mask 
has  to  be  changed  to  modify  the  circuit.  Furthermore,  the  specific 
layout  of  the  chip  can  be  done  by  the  practicing  circuit  engineer  using 
only  a few  guidelines. 

This  report  summarizes  the  background  information  that  a circuit 
engineer  requires  to  proceed  with  the  design  of  a custom  digital  LSI 
using  a complementcury  MOS  (CMOS)  gate  array. 


2 . DEVICE  OPERATION 

A cross-sectional  view  of  a P-channel  MOS  FET  is  shown  in 
figure  1(a).  The  metal  is  aluminum,  the  oxide  Si02,  and  the 
semiconductor  silicon.  Source  and  drain  are  Interchangeable,  The 
device  works  as  follows:^  It  is  biased  so  that  the  junctions  formed  at 


^S.  S,  Eaton,  Timekeeping  Revolution  through  COS/MOS  Technology,  RCA 
COS /MOS  Technology  (1973),  33-41. 

^D.  K,  Morgan,  COS/MOS  Integrated  Circuits  in  the  Automobile 
Environment,  RCA  COS/MOS  Technology  (1973),  45-51. 

^R.  A.  Bishop  and  D.  R.  Carley,  Fundamentals  of  COS/MOS  Integrated 
Circuits,  RCA  COS/MOS  Technology  (1973),  8-11. 


5 


OUTPUT 


0.0002  IN. 


SUBSTRATE 


DEPLETION  REGION 
BACK  BIASED 

+V 

(a) 

GATED  OFF 

-V 

-V 

OUTPUT 

DEPLETION  REGION  'P-CHANNEL 

(b)  GATED  ON 


SOURCE 


T 


(c)  SYMBOL 


DRAIN 


Figure  1.  P-channel  MOS  FET. 


the  P'^-N  silicon  Interfaces  are  either  back  biased,  at  zero  bias,  or  in 
between.  They  draw  no  current  A) . The  normal  minority  carrier 
injection  mechanism  for  tremsistor  operation  Is  not  used.  Instead,  when 
a negative  voltage  Is  applied  to  the  gate,  as  shown  In  figure  1(b),  the 
high  field  effect  through  the  thin  oxide  forces  holes  to  be  attracted  to 
the  surface  of  the  N-type  silicon  under  the  gate.  This  field  causes  a 
thin  channel,  which  Is  doped  like  P-type  silicon,  to  exist  and  maikes  a 


thin  depletion  region  below  it  that  now  includes  both  junctions. 
Current  is  edsle  to  flow  between  source  and  drain.  The  resistemce  of  the 
P-channel  is  typically  1000  ohms  for  a 0 . 001-in . -wide  channel 
(X  0.002-in.  long).  The  gate  has  a capaclt2mce  of  about  0,4  pF,  while 
the  source  and  drain  each  have  about  0.1  pF  for  P-channel  and  0,2  pF  for 
N-channel  devices.  Because  the  depletion  region  surrounds  the 
conductive  region,  no  current  flows  into  the  substrate,  and  the  active 
region  is  well  Isolated  from  other  active  devices  on  the  same  substrate 
(very  important  in  integrated  circuits) . 

To  keep  the  leakage  current  low  when  no  gate  voltage  is  applied,  the 
silicon  surface  must  be  very  pure,  because  the  depletion  region  comes  up 
to  the  surface  edge.  Any  surface  Impurities  Increase  the  le£dcage 
current.  The  CMOS  is  specified  at  less  than  10  nA  (10“®  A)  and 
typically  has  0.1  to  1 nA  (10"^®  to  10~^  A).  A value  of  about  10"**  is 
required  for  digital  circuit  operation  where  each  gate  is  allowed  to 
dissipate  1 mW.  A chip  with  1000  gates  might  rather  be  limited  to 
10“^  A to  avoid  heat-sinking  problems. 

The  gate  voltage  required  to  attract  enough  holes  to  the  surface  to 
make  a conductive  P-channel  is  called  the  threshold  voltage.  This 
voltage  is  determined  by  the  built-in  potential  of  the  silicon  surface 
under  the  gate,  by  the  thickness  and  dielectric  constant  of  the  oxide, 
and  by  the  doping  density  of  the  N-type  sxibstrate.  The  thinner  the 
oxide  or  the  higher  its  dielectric  constamt,  the  lower  the  threshold 
voltage.  It  also  takes  a very  strong  field  to  attract  enough  holes  to 
convert  heavily  doped  N-type  semiconductor  to  P-type  with  mobile 
carriers  as  required  for  the  channel.  Therefore,  the  lower  the  doping 
density  of  the  N-type  material,  the  lower  the  threshold  voltage.  These 
factors  combine,  forcing  a compromise  threshold  voltage  of  1 to  2 V. 

The  FET  as  described  is  an  enhancement-mode  tramsistor.  It  is 
nonconductive  unless  a gate  voltage  is  applied.  By  arramging  doping 
densities,  a depletion-mode  FET  cam  be  made,  but  it  does  not  have  the 
low-power-consumption  properties  of  enhamcement-mode  tr^sistors.  Care 
must  be  exercized  in  fadsrlcating  FET's  that  impurities  are  not 
introduced  on  the  surface.  These  impurities  can  move  the  threshold 
voltage  and  increase  the  leakage  current.  Moving  the  threshold  voltage 
cam  change  an  enhancement-mode  transistor  to  depletion  mode  and  cam 
change  the  gain  characteristics,  frequency  response,  and  immunity  to 
noise. 

The  symbol  for  the  enhancement-mode,  P-channel  FET  is  shown  in 
figure  1(c).  The  arrow  points  to  the  N-most  material,  which  in  this 
figure  is  the  substrate.  In  an  N-channel  device,  the  arrow  points  to 
the  channel.  The  bias  voltage  is  applied  in  the  polarity  to  back  bias 
the  diode  if  the  symbol  were  to  represent  a diode.  The  P in  the  symbol 


7 


may  be  anywhere  in  the  region  of  the  source-channel-drain  area  and 
represents  the  polarity  of  the  channel.  Sometimes  the  arrow  or  letter 
is  omitted.  The  source  and  drain  are  Interchangeable.  The  line 
connecting  source  and  drain  should  be  shown  as  a broken  line  for 
enhemcement-mode  FET's  and  as  a solid  line  for  depletion-mode  FET*s, 
Very  little  use  is  made  of  depletion-mode  FET's  in  digital  circuits  as 
active  devices,  so  they  are  seldom  seen,  and  frequently,  authors  show  a 
solid  line  for  enhancement-mode  FET's,  It  is  best  to  assume  that  an  FET 
is  an  enh2uicement-mode  device,  unless  there  is  some  statement  to  the 
contrary. 

In  the  CMOS,  there  are  an  equal  number  of  P-channel  and  N-ch2umel 
FET's,  Figure  1(a)  and  (b)  could  be  used  to  describe  an  N-ctumnel 
device  by  switching  P and  N and  + and  -,  The  mobility  of  the  carriers  in 
an  N-chemnel  is  about  twice  as  high  as  for  the  P-channel;  therefore,  the 
P-chemnels  are  made  about  twice  as  wide  to  keep  the  output  impedances  of 
the  two  devices  equal. 

The  dc  characteristics  of  a typical  N-channel  MOS  FET  are  shown  in 
figxire  2. 


Figure  2.  MOS  FET  voltage-current  charteristics. 


. I 


I 


8 


3 , CIRCUIT  OPERATION 


3,1  Inverter 

The  most  basic  circuit  using  a CMOS  PET  pair  is  shown  in 
figure  3(a),  Conventionally,  the  P’-cheinnel  FET  is  at  the  top  with  its 
substrate  connected  to  +V,  and  the  N-chamnel  FET  is  at  the  bottom  with 
its  substrate  connected  to  ground.  Inputs  and  outputs  are  between  0 and 
+v.  The  +V  is  a "1"  or  HI  and  0 (ground)  is  a "0"  or  LO,  When  is 
0 V,  the  N-chemnel  FET  (fig.  3(a),  lower  transistor)  has  no  field 
induced  by  the  gate,  and  it  is  OFF  (nonconductive) , The  P-channel  FET 
(fig,  3(a),  upper  transistor)  has  a relative  -V  applied  to  the  gate  tin 
the  back  bias  polarity  if  it  were  a diode) , and  therefore  it  is  forced 
into  the  conduction  state.  Since  the  source  is  connected  to  +V,  tlie 
output  is  +V  (HI) , 


N I ''out 
SOURCE  O 


GATE  I CHANNEL 


(a)  CMOS  PAIR 


HIpj'.  P-CHANNEL  O CONDUCTIVE  “ON 

'x'  Hf  WHEN  CONNECTED 

' n',  "TO 

IN  OUT 


CO  N-CMANNEL  '*0  CONDUCTIVE  - ON 

LO  WHEN  CONNECTED 
TO  (3ROLNO 

(b)  SWITCHING  SENSE  OF  CMOS  PAIR 


Figure  3.  CMOS  pair  operation. 


9 


When  is  +V,  then  there  is  no  high  field  on  the  P-channel 
FET,  and  it  is  OFF.  The  N-clumnel  FET  is  (back)  biased  so  that  it  is 
conductive.  Since  its  drain  is  connected  to  ground,  V is  LO.  The 
operation  of  this  circuit  can  be  visualized  as  shovm  iS'^^figure  3(b). 
Since  the  circuit  changes  LO  to  HI  and  HI  to  LO,  it  is  an  inverter  or 
a logic  NOT  gate. 

The  voltage-current  characteristics  of  the  inverter  are  shown 
in  figure  4.  This  inverter  has  several  in^rt2mt  properties  when  used 
in  digital  circuits.  The  voltage  input-output  is  nonlinear  so  as  to 
improve  the  squareness  of  input  pulses.  This  nonlinearity  helps  O's  to 
stay  O's  and  I's  to  stay  I's,  mcikes  the  output  more  binary,  and  improves 
the  immunity  to  noise  of  the  logic  circuit.  The  nonlinearity  is  well 
shaped  for  a wide  remge  of  power-supply  voltages.  A regulated  power 
supply  is  not  required  to  operate  these  circuits;  a given  circuit  can  be 
operated  satisfactorily  over  the  wide  reuige  of  power-supply  voltages. 
The  sacrifice  made  for  lower  voltages  is  slower  speed,  because  the 
conductivity  of  the  channel  is  not  raised  as  high  by  the  lower  gate 
voltage . 


Figure  4.  Inverter  voltage-current  characteristics. 


The  second  property  is  that  the  circuit  draws  current  only  in 
the  transition  from  the  0 to  the  1 state  and  vice  versa — during 
switching.  In  the  fully  switched  state,  the  circuit  draws  only  leakage 
current,  permitting  logic  to  be  held  at  very  low  sustenemce  power 
levels.  This  low  power  consultation  saves  power-supply  energy  and 
permits  the  FET's  to  be  densely  packed,  since  they  are  not  generating 
much  heat. 


10 


Third,  the  CMOS  FET's  can  be  connected  directly  to  each  other, 
requiring  no  additional  resistors,  capacitors,  or  inductors.  Therefore, 
they  can  be  easily  connected  together  to  medce  an  Integrated  circuit. 
Also,  the  output  impedance  is  about  1000  ohms,  while  the  input  impedance 
is  capacitive  (the  gate  capaclt^ulce) . Therefore,  one  FET  can  drive  a 
large  number  of  other  FET's — fan  outs  up  to  2Qx>ut  50. 

The  limits  on  fan  out  and  loading  of  FET's  are  set  by  the 
switching  speed  and  power  dissipation  that  cam  be  tolerated.  The 
capacitances  of  output  lines  and  input  gates  are  added  up  to  determine 
the  capacitive  load.  The  1000-ohm  output  iiti)ed2mce  and  this  capaciteuice 
determine  the  RC  time  constant  for  propagation  delay.  A typical 
propagation  delay  is  25  ns.  The  power  dissipation  is  given  by  cv"f , in 
which  C is  the  total  capacitamce,  V is  the  supply  voltage,  and  f is  the 
data  rate  frequency.  The  power  dissipation  of  a gate  for  several 
typical  voltages  and  loads  is  shown  in  figure  5,  A typical 
transistor-transistor  logic  (TTL)  gate  rec[ulres  7,5  mW  with  a speed  of 
12  ns.  Thus,  the  CMOS  consumes  less  power  for  average  switching  rates 
on  an  array  of  less  than  several  meg^dlertz, 


Figure  5.  Power  dissipation. 


3,2  Transmission  Gate 

The  second  basic  building  block  for  digital  logic  using  CMOS 
FET's  is  the  transmission  gate.  The  FET's  are  arranged  as  shown  in 
figure  6(a).  The  gate  works  ^n  either  direction.  It  is  turned  on  bjr 
the  positive  clock  pulse  C,  C is  the  complement  of  the  clock  pulse  (C 
is  normally  1,  0 during  the  clock  pulse).  Normally,  the  N-channel  FET 
has  a 0 on  the  gate,  and  the  source  and  drain  are  not  conductively 
connected.  The  presence  of  a clock  pulse  puts  a 1 on  the  N-channel  FET 
gate,  providing  the  high  electric  field  that  produces  the  conductive 
path  between  source  and  drain,  turning  ON  the  FET.  In  a similar  manner, 


p = I — OFF 
V =0— ON 


r =0  — OFF 
= I —ON 


(o)  NORMALLY  OPEN  CMOS  GATE 


-Llg—I- 


NORMALLY  OPEN  ^ 

ON  WHEN  CLOCK  PULSE  IS  PRESENT  — O — 


H tg  h 


normally  on 

OPEN  (OFF)  WHEN  CLOCK  PULSE  IS 
PRESENT 


(b)  SYMBOLS  FOR  CMOS  GATE 


Figure  6.  CMOS  transmission  gate. 

the  P-channel  PET  is  turned  ON  by  C during  the  clock  pulse.  Both  FET's 
are  necessary  to  obtain  conduction  for  all  V where  0 < V < +V,  For 
subsequent  discussion,  transmission  gates  are  represented  by  the  symbols 
shown  in  figure  6 (b) . 

Transmission  gates  are  normally  used  in  complementary  pairs 
with  a common  input  or  output.  This  is  the  function  of  the  single-pole 
double-throw  (SPDT)  switch  as  shown  in  figure  7.  This  is  also  an  analog 
switch,  since  the  linearites  of  A and  B are  preserved  under  normal 
switching  conditions. 


12 


i 


3.3  Logic  Gates 

The  truth  tcible  and  layouts  using  the  CMOS  for  various  logic 
gates  are  shown  in  figure  8. 

An  AND  circuit  produces  a HI  output  only  if  all  of  the  inputs 
are  HI.  Since  one  stage  of  CMOS  produces  a logic  sense  inversion,  the 
NAND  is  the  more  basic  circuit,  and  the  unique  output  is  LO.  Since  the 
N-chauinel  FET's  produce  LO  output  when  they  are  conductive,  they  are 
placed  in  series  in  the  NAND  circuit  so  that  the  output  is  LO  only  when 
all  of  the  inputs  are  HI.  (Recall  from  figure  3(b)  that  a HI  input 
forces  the  N-channel  FET's  into  conduction,  whereas  a LO  input  forces 
the  P-channel  FET's  into  conduction.)  Since  the  NAND  output  should  be 
HI  for  all  other  input  conditions,  the  P-channel  FET's  are  placed  in 
parallel  as  shown  in  figure  8 . 

An  OR  circuit  produces  a HI  output  if  any  one  of  the  inputs  is 
HI.  The  NOR  thus  produces  a LO  output  when  any  one  of  the  inputs  is  HI. 
To  get  a LO  output  most  of  the  time,  the  N-channel  FET' s must  be  placed 
in  parallel  as  shown  in  figure  8.  Since  the  NOR  output  should  be  HI 
only  when  all  of  the  inputs  are  LO,  the  P-channel  FET's  are  placed  in 
series. 


The  operation  of  the  NOT  circuit  was  discussed  with  figure  3, 
When  AND  or  OR  logic  functions  are  required  with  CMOS,  a NOT  is  added  to 
a NAND  or  NOR. 

In  figure  8,  the  little  circles  at  the  output  or  input  of 
logic  symbols  indicate  logic  inversion  (the  NOT  function) , Logic 
inversion  of  a variable  is  indicated_by  a bar  over  the  variaUale  or  by  a 
prime  on  the  variable.  For  exeunple,  B or  B'  is  called  "not  B," 


■ 

I 


I 

4 


I 


13 


o ♦v 


A A 
0 0 
0 1 
I 0 
I I 


JjOR_ 

A+~B 

I 

0 

0 

0 


NAIMD 

A B 


Figiire  8.  CMOS  logic  circuits. 


4 . LOGIC  CIRCUITS 

4,1  Memory  Element/Shift  Register 

For  a CMOS  gate  to  stay  latched  in  a state,  its  input  must  be 
tied  to  another  CMOS  in  a way  that  provides  regenerative  feedback.  The 
combination  of  NOT  gates  and  transmission  gates  shown  in  fig\u:e  9 
provides  this  condition.  Since  TG  is  normally  closed,  the  master 
section  tracks  the  data  voltage  (D)  until  a clock  pulse  comes  along.  At 
the  leading  edge  of  the  clock  pulse,  TG  closes,  and  the  master  loop  is 
latched  into  the  new  D state  existing  during  latching.  Since  thejslave 
input  TG  is  closed  also  by  the  leading  edge  of  the  clock  pulse,  D (the 
output  of  the  master)  is  fed  to  the  slave  circuit.  At  the  end  of  the 
clock  pulse,  the  master  is  still  in  its  latched  state  so  that  when  the 
TG  input  to  the  slave  opens,  that  state  is  retained  by  the  slave 
circuit.  Through  the  clock  cycle,  the  input  logic  state  D has  been 
transferred  from  the  input  of  the  master  loop  to  the  output  of  the  slave 
loop.  The  slave  loop  retains  its  logic  state  until  another  clock  pulse 
comes  along.  The  slave  loop  by  Itself  is  the  smallest  memory  element. 
This  positive  clock  shift  register  element  (or  basic  D-type  flip-flop) 
is  leading-edge  triggered  logic.  By  lnterch£mglng  TG  and  TG,  it  is  made 
into  trailing-edge  logic  (negative  clock) . 


MASTER 


Figure  9.  Shift  register;  basic  D-type  flip-flop 
(positive  clock) . 

These  shift  registers  can  be  added  in  series  for  providing 
logic  delay  or  for  decoding  a serial  bit  word  of  any  length.  The  serial 
bit  word  comes  in  on  one  line  and  is  converted  by  the  shift  register  to 
a parallel  line  output  in  a hold  state  to  be  used  by  the  other  logic. 
The  clock  is  applied  to  the  shift  register  only  when  the  word  is  coming 
in.  This  is  a serlal-ln,  parallel-out  decoder. 


Presettable  D-1 


Flip-Floi 


A parallel-in,  serial-out  decoder  can  be  made  by  replacing  the 
NOT  gates  by  two-input  NOR  gates  as  shown  in  figure  10.  Then  the  shift 
register  element  can  be  preset,  and  when  the  clock  is  applied,  the 
serial  word  is  shifted  out  to  the  right.  In  figure  10,  buffer  outputs 
are  shown  added  to  maintain  fast  switching  when  required. 


R -»Q.O  0 + CI  — 0 + l = D 


Figure  10.  Presettad>le  D-type  flip-flop  (positive 
clock) . 

4.3  Frequency  Divider 

A frequency  divider  (scale-of-two  counter)  is  made  by  feeding 
the  inverted  slave  output  of  a shift  register  circuit  back  into  the 
master  as  shown  in  figure  11.  The  input  to  the  divider  is  the  clock, 

and  the  output  provides  the  clock  for  the  next  divider  stage.  The 
counter  can  be  made  presettadile  by  use  of  NOR  gates  in  place  of  NOT 
gates,  as  is  done  for  the  D-type  flip-flop. 


J-K  Flip-Flop 


The  J-K  flip-flop  (fig.  12)  has  two  data  inputs.  When  J or  K ! 
is  HI  during  a clock  pulse,  J sets  the  output  HI,  or  K sets  it  LO  I 
(reset).  When  both  J and  K are  LO  during  a clock  pulse,  the  logic  state  I 
of  the  output  is  not  changed.  When  J and  K are  HI  during  a clock  pulse, 

the  logic  state  of  the  output  is  changed  to  the  other  state.  It  is  t 
basically  a D-type  flip-flop  with  additional  logic  to  handle  the  two  | 
inputs  and  their  relationship  to  the  previous  output.  I 


5.  DERIVING  LOGIC  CIRCUITS  FROM  TRUTH  TABLES 
5.1  Truth  Table 

A truth  table**  shows  the  output  of  a circuit  for  all  possible 
combinations  of  the  Inputs.  A D-type  flip-flop  is  converted  to  a J-K 
flip-flop  by  the  addition  of  some  logic  to  the  input.  This  input  logic 
circuit  serves  as  an  exasqple  to  show  how  a truth  tzdile  leads  to  a logic 
circuit. 

Based  on  the  description  of  the  operation  of  a J-K  flip-flop 
just  given,  the  truth  table  shown  in  figure  13  is  derived.  Q is  the 
previous  output  of  the  D-type  flip-flop  as  shown  in  figure  12,  D is  the 
new  input  to  the  D-type  flip-flop. 

J K Q I D 
0 0 0 0 
10  0 I 


0 

I 

0 

I 

0 

I 


I 

I 

0 

0 

1 

I 


0 


0 


0 

I 

I 

I 

I 


I 

1 

I 

0 

0 


0*  J K'Q'  + J KQ'  + J'K'Q  + JK'Q 
D'=  J'K'Q'  + J'KQ'  +J'KQ  +JKQ 

Figure  13.  J-K  input  truth  table  (to  D-type  flip 
flop) . 


The  czuionical  logic  expressions  for  the  table  also  are  shown  in 
figure  13.  Primed  letters  are  in  the  inverse  logic  state  of  unprimed 
letters.  Either  equation  gives  the  function.  The  D eqxiation  is  derived 
by  taking  the  rows  for  which  D is  1.  The  first  term  produces  a logic  1 
when  J » 1 AND  K'  » 1 (K  = 0)  AND  Q'  •*  1(Q  ■=  0).  The  other  terms  are 
slmllzurly  composed.  VAien  any  one  of  the  terms  is  one,  then  D 1,  Each 
term  is  thus  a product  and  cam  be  realized  by  using  a three-input  AND 
circuit  (fig,  8) . The  sum  of  the  terms  is  an  OR  function,  which  can  be 
realized  by  connecting  the  output  of  the  AND  circuits  to  a four-input  OR 
circuit.  The  output  of  the  OR  circuit  provides  the  logic  state  D, 


**A,  B,  Marcovitz  a.id  J.  M.  Pugsley,  Introduction  to  Switching  System 
Design,  John  Wiley  and  Sons,  Sew  York  (1971). 


17 


Sometimes  it  may  be  more  convenient  to  use  the  second  equation^ 
Instead,  Each  term  is  made  up  by  using  AND  circuits  as  before , but  to 
get  D as  an  output,  a NOR  circuit  instead  of  an  OR  circuit  is  used  for 
combining  them. 

The  equations  of  figure  13  do  not  use  the  minimum  nuniber  of 
logic  elements.  These  algebraic  equations  can  be  sin^lified  by  using 
Booleem  algebra  or  some  teUaular  constructs  such  as  a Don't  Care  table  or 
a Karnaugh  map. 


5.2  Boole«ui  Algebra 

The  more  useful  basic  relationships  of  Boolean  algebra  are 
I shown  in  figure  14.  Either  primes  or  bars  can  be  used  to  denote  an 
opposite  state.  Normally,  beurs  are  used  to  denote  it  in  logic  diagrams. 
DeMorgan's  Theorem  can  be  stated  as  "The  NOT  of  the  sum  is  equal  to  the 
product  of  the  NOT's"  or  "The  NOT  of  the  product  is  equal  to  the  sum  of' 
the  NOT's."  This  theorem  is  useful  in  converting  logic  circuits  to 
NOR's  and  NAND's  as  required  for  CMOS  LSI.  The  equations  of  figure  13 


1,  X=  EITHER  I OR  0 

2.  X'=  OPPOSITE  STATE  OF  X 

3 X + Y = 0 ONLY  IF  BOTH  =0  qR 
XY=I  ONLY  IF  BOTH  = I AND 

4.  ASSOCIATIVE  (X+Y)  + 2=  X + ( Y + Z) 

(XY)Z=  X(YZ) 

5.  ABSORPTION  X + X = X 


X X = X 

6.  COMMUTIVITY  X+Y  = Y + X 
XY=  YX 

7 X + 0 = X X I = I 

8.  X 0 = 0 X + I = I 

9.  X + X'  = l X X'»0 

IQ  DISTRIBUTIVE  X(Y+Z)=XY  + XZ 

X + YZ  *(X  + Y)(X-I-Z) 


II  X + XY  = X 
X(X+Y)*X 
12.  X + X'Y  = X + Y 
X(X'+Y)  = XY 


13 

14 


(X')'  = X 

(X,  +x,+  +x„)'=  x;  X, 


(X,X2  Xm)'*X;+X2+  +X|^ 


DE  MORGAN'S 
THEOREM 


Figure  14.  Boolean  algebra. 


18 


could  be  sln^llfled  by  use  of  Boolean  algebra,  but  unless  a logic 
designer  is  fzunlllar  with  the  basic  relationships  and  the  standard 
tricks  for  mwipulating  them,  the  algebraic  reduction  is  very  tedious 
and  subject  to  error.  Fortxinately,  some  tabular  constructs  (e.g..  Don't 
Care  tables  and  Karnaugh  maps)  permit  direct  reduction  quite  simply  when 
the  number  of  input  variables  is  not  too  high.  Con^uter  programs  are 
availed^le  to  reduce  the  equations  for  digital  logic  and  are  almost  a 
must  for  logic  having  five  or  more  input  variables. 

5.3  Don't  Care  Table 

Don't  Care  tedsles  for  the  J-K  input  truth  table  are  shown  in 
figure  15.  In  the  upper  example,  the  "1"  rows  are  arranged  that  provide 
D.  The  rows  are  paired  up  so  that  those  that  are  different  for  only  one 
input  V2u:lable  are  together.  Since  the  output  is  a "1"  Independent  of 
the  state  of  that  input,  the  output  is  "don't  care."  It  is  only  a 
function  of  the  other  input  v£u:ied}les.  In  like  manner,  the  lower  table 
provides  D'  in  a reduced  algebraic  form.  These  equations  are  equivalent 
to  those  given  in  figure  13  and  could  have  been  derived  by  using  Boolean 
algebra  as  defined  in  figure  14.  The  shorter  equations  require  fewer 
logic  elements. 


D = JQ'  + K'Q 


D'=  j'0'+  KQ 


Figure  15.  "Don't  Care"  tables. 


iir 


5,4  Karnaugh  Map 

A systematic  arr2mgement  for  putting  input  logic  statements 
next  to  each  other  that  are  different  in  only  one  term  is  the  Karnaugh 
map  as  shovm  in  figure  16.  It  is  easily  constructed  in  two  dimensions 
for  up  to  four  input  variables.  The  J-K  colximn  is  rolled  through,  in 
that  each  row  is  different  from  the  other  in  only  one  digit.  Also,  the 
bottom  can  be  rolled  onto  the  top  in  the  same  manner.  If  there  were 
four  input  variediles,  there  would  be  four  rows  of  possible  outputs 
(Instead  of  two) , and  the  indexing  of  these  rows  would  be  rolled,  as 


well.  In  finding  reduced  solutions,  the  I's  or  O's  are  grouped  in  one 
or  two  dimensions  in  groups  of  two  or  four  on  a side.  The  larger  the 
group,  the  sin^ler  the  logic  expression  to  provide  the  function.  Any 
element  Cem  belong  to  more  than  one  group,  to  Include  all  elements  in 
groups  and  provide  the  simplest  logical  expression.  The  Karnaugh  map 
provides  the  same  equations  as  the  "Don't  Care"  tediles  of  figure  15. 


J 

0 1 

0 0 
0 1 
1 1 
1 0 

•O'  U 
'21  1^1 

ai 

Lq'JLqJ 


K' 

J 

T 


J 

T 

K' 


D*  J0*+K‘Q 
D'*  J‘Q'+  KQ 

Figure  16.  Karnaugh  map. 


5,5  Converting  to  NCR's  amd  HAND'S 

The  statement  of  DeMorgem's  Theorem  for  two  input  viuriables  is 
shown  in  figure  17(a).  The  logic  symbol  representation  of  it  is  shown 
below  the  equation.  Adding  a MOT  circuit  to  the  output  of  each  circuit 
produces  the  symbol  equivalence  shown  in  figure  17(b),  The  other 
statement  of  DeMorgem's  Theorem  and  its  developed  symbol  equivalence  are 
shotm  in  figure  17(c).  These  equivalences  apply  for  any  number  of 
inputs  as  indicated  in  eqxiations  (14)  in  figxire  14. 


20 


A+  B = A B 


(ai  s ::33- 

(b)  = 43^ 

A~B  = A+ B 

Figure  17.  DeMorgan's  Theorem. 


With  the  identies  shovm  in  figure  17,  all  OR's  and  AND's  in  a 
logic  diagram  can  be  converted  to  NAND's  and  NOR's  to  minimize  the 
number  of  inverters  required  in  using  CMOS  LSI. 

An  easy  way  to  visualize  the  identities  is  to  consider  the  OR's 
and  AND ' s as  plump  chickens . They  Ccm  be  converted  respectively  to 
NAND's  and  NOR's  by  having  the  appropriate  tight  girdle  put  on  them. 
The  girdle  is  so  tight  that  it  causes  the  chicken  to  lay  an  egg  (at  the 
output)  and  her  eyes  to  bulge  out  (at  the  inputs) . The  input  and  output 
circles  are  NOT's  that  Ceui  be  pushed  to  either  end  of  a connecting  line. 
Two  NOT's  cancel,  or  a NOT  can  be  pushed  through  a logic  symbol  by  being 
chemged  as  shown  in  figxire  17(a).  To  convert  a logic  diagram  to  NAND's 
and  NOR's,  every  other  logic  element  should  thus  be  converted  by  using 
DeMorgcin's  Theorem.  The  NOT's  are  then  moved  aroxuid  so  that  they  are  on 
the  outputs  of  all  of  the  logic  syn±>ols.  If  any  are  left  over,  they  cam 
be  camceled  out  by  having  NOT  logic  elements  (inverters)  added  as  shown 
in  figure  8. 

When  these  trams formations  are  applied  to  the  equations  for  the 
J-K  flip-flop  input,  the  logic  diagrauns  evolve  as  shown  in  flg\ire  18. 
Either  logic  circuit  provides  the  desired  function.  Both  taJce  J and  K 
as  Inputs  and  require  the  same  nundser  of  CMOS  LSI  transistors.  The 
difference  between  them  is  the  input  Q.  The  choice  of  circuit  should  be 
based  on  which  form  of  Q is  most  readily  available,  Q or  Q* . 


21 


D'JO'  + K'C  D'»J'o'  + KO 


Figure  18.  Evolution  of  J-K  flip-flop  input 
logic  circuits. 


6.  CMOS  LSI  GATE  ARRAY 

Normally  when  a custom  LSI  is  made,  first  the  arrangement  and 
Interconnection  of  tremsistors  is  laid  out.  Provision  is  made  for 
supply  voltage,  for  input-output  buffering,  and  for  bonding  pads.  Then 
seven  or  more  masks  are  generated  for  diffusing  the  dopants  into  the 
semiconductor,  for  creating  insulating  layers  of  oxide,  and  for 
metalizing  the  final  surface.  The  layout  of  new  masks  produces  problems 
in  that  the  parasitic  coupling  between  close  elements  can  produce 
deleterious  electrical  effects,  or  heat  production  in  a given  area  might 
be  high,  causing  undesirable  electrical  perfoinricmce  and  reduced  useful 
life.  When  a circuit  is  chcmged,  all  seven  or  more  masks  must  be 
changed,  and  many  of  the  initial  problems  must  be  solved  again.  Only 
after  a circuit  has  been  produced  in  substantial  quamtitles  and  has 
acquired  a successful  use  history  cam  it  be  considered  as  a reliable 


22 


1 


integrated  circuit.  These  attributes  of  "normal"  integrated  circuits 
lead  to  high  initial  cost,  high  cost  of  change,  and  a delayed  and 
initially  uncertain  certification  of  reliability.  Only  when  an 
integrated  circuit  is  going  to  be  used  in  large  qu2mtlties  or  when 
space,  weight,  or  reliability  is  at  a premium  is  it  practical  to  develop 
custom- Integrated  circuits. 

Signific2int  advcmces  have  been  made  in  the  technology  reducing  the 
initial  cost  and  risk  of  custom- integrated  circuits. Con^uter 
programs  have  been  developed  to  model  parasitic  and  thermal  effects. 
Other  programs  have  been  developed  to  do  placing  and  routing.  Once  the 
placing  and  routing  are  in  the  computer  memory,  still  other  programs  can 
automatically  generate  the  masks.  By  using  these  programs,  tvimaround 
costs  and  risk  are  reduced  significantly.  To  some  extent,  the  product 
is  lower  in  cost  and  initially  more  relledjle,  based  on  the  substantial 
output  cuid  use  history  of  the  computer  programs  and  associated 
fcdsrication  processes  (ongoing  production) , These  advances  in 
automation  have  reduced  the  quantities  or  premium  required  to  justif;^ 
customizing  Integrated  circuits,  but  another  technique  of  making 
custom- Integrated  circuits  reduces  them  even  more. 

This  technique  uses  an  LSI  array  of  transistors  and  required  biasing 
and  interconnecting  parts.  The  semiconductor  chip  Is  up  to 
0.3  in.  square  and  contains  up  to  1104  transistors.  The  TTL  is 
available  with  up  to  210  gates,  CMOS  with  up  to  276  gates  (actually  1104 
tr^mslstors  to  be  connected  any  way) , and  tr2Uisistor-resistor  logic  with 
up  to  400  gates.  The  gate  arrays  are  produced  Initially  with 
metalization  covering  the  surface.  For  a custom  design,  one  mask  is 
made  that  defines  the  metal  to  be  etched  away  where  it  is  not  desired, 
The  remaining  metal  forms  the  custom  Interconnecting  pattern  and  bonding 
pads. 

The  same  array  chip  can  be  used  for  many  different  circuits; 
therefore,  only  one  set  of  diffusion  masks  needs  to  be  developed,  and  it 
has  to  be  proved  out  only  once.  The  tr£msistors  are  spread  out 
uniformly,  therefore  reducing  problems  o^  electrical  interaction  and 
localized  heating.  When  a circuit  is  designed,  only  one  mask  needs  to 
be  made,  significantly  reducing  engineering  cost  and  complexity.  When  a 
circuit  is  changed,  only  one  mask  needs  to  be  changed.  Bonding  pads  and 
packaging  are  also  standardized  for  a given  array  chip,  reducing  the 


T.  Doyle  and  C.  A.  Neugebauer,  Approaches  to  Custom  Large  Scale 
Integration,  General  Electric  Company,  Schenectady , NY^  AFAL~TR~7 3~66 
(March  1973). 

^ ^R.  O,  Berg  et  al.  Approaches  to  Custom  LSI,  Honeywell,  Inc., 

AFAL-TR-7 3-16  (April  1973) . 

i 


f 

! 


23 


reliability  hazards  normal  in  new  fabrication  processes.  The  advantages 
of  array  chips  are  that  LSI*s  can  be  designed  at  the  engineering  level 
simply  and  inexpensively,  leading  to  low  initial  cost,  low  change  costs, 
and  quick  design  turnaround,  and  that  many  of  the  failure  mechanisms 
that  lead  to  poor  reliability  in  new  circuits  are  reduced  by  the 
similarity  in  fabrication  for  all  LSI's  using  the  same  basic  array  chip. 
The  disadvantage  of  using  array  chips  is  that  a truly  handcrafted  custom 
LSI  could  put  twice  the  number  of  circuits  on  the  same  chip.  This 
better  use  of  space  leads  to  lower  unit  costs  and  smaller  volume. 
Therefore,  when  a large  number  of  units  is  to  be  produced  or  where 
volume  is  at  a high  enough  premium,  the  high  initial  cost  of  handcrafted 
custom 'LSI’s  is  warranted.  For  fabrication  of  10^  units,  the  array  is 
favored.  For  fabrication  of  10®  units,  custom  handcrafting  is  favored 
(J.  Saultz,  private  communication) . 

The  RCA  TCC  051  CMOS  array  is  shown  in  figure  19.  The  chip  is 
0,30  in.  square  and  contains  1104  FET's,  48  input-output  bonding  pads, 
input-output  protection  circuits,  buried  interconnection  and 

supply-voltage  channels,  and  chip  test  devices.  Nine-hundred-sixty 
FET's  are  considered  internal  to  the  chip,  and  the  remainder  are  around 
the  edge  for  input-output  interfacing  or  for  special  impedance  levels. 
For  a given  cross  section  of  an  FET  as  shown  in  figure  1,  the  "on" 
admittance  level  is  proportional  to  the  length  of  the  source/drain  gate. 
The  internal  FET's  are  about  1000  ohms  when  conducting,  whereas  the  96 
FET's  associated  with  the  input-output  pads  are  about  500  ohms.  Also, 
16  low-inqpedamce  FET's  ('vSO  ohms)  and  32  high-iropedauice  FET's 
(<^10,000  ohms)  are  around  the  periphery  of  the  chip. 

The  basic  internal  cell  of  the  array  is  shown  in  figure  20.  It 
consists  of  two  P-chamnel  MOS  FET's  and  two  N-channel  MOS  FET's,  each 
pair  with  a common  source/drain.  Supply  voltages  are  made  available 
near  the  points  most  likely  to  need  them,  and  a few  burled  crossover 
chzuinels  are  made  available  for  crossing  lines.  Printed  lines  are  made 
0.0004  in.  wide  and  are  on  0.0008-in.  centers  as  Indicated  by  the 
overlay  matrix  of  dots.  This  cell  layout  is  easily  used  for  m2d(lng 
logic  circuits  as  shown  by  the  exeunples  given  in  figure  21.  Because  the 
treuislstors  come  in  pairs  (with  a common  source/drain) , a single 
transmission  gate  is  not  easily  made  by  itself  without  rendering  a 
j complementary  pair  of  transistors  (one  P-chamnel  and  one  N-channel) 

useless.  The  basic  cell  in  this  array  provides  two  transmission  gates 
in  an  SPOT  switch  arrangement.  Fortunately,  tramsmission  gates  are  used 
mostly  in  pairs  as  in  figures  9 to  12. 

When  speed  or  large  fan  out  is  required,  the  resistance  and 
capacltcmce  of  Interconnecting  lines  and  crossover  channel  must  be  taken 
into  accovmt. 


24 


Figure  20.  RCA  CMOS  cell. 


bIO-” 


Figure  21.  Two-input  NAND  and  NOR  gates. 


( 


■1.'  - 


27 


c 


with  the  above  background.  It  should  be  possible  to  begin  the  CMOS 
LSI  array  design  and  fed^rication:  (1)  Reduce  the  entire  logic  to 
diagram  using  NCR's,  NANDS's,  NOT's  and  tramsmission  gates.  (2) 
Partition  the  circuit  counting  up  the  number  of  input-output  pads 
required  for  each  chip  including  bias  requirements,  to  be  sure  that  the 
maximum  number  for  each  chip  is  not  exceeded,  and  leaving  ahoxit 
20  percent  of  unused  cells.  (3)  Lay  out  the  chips,  avoiding  long  or 
"heavy"  interconnecting  lines,  to  be  sure  that  the  series  resistance  or 
loading  capacitance  will  not  slow  down  the  logic  too  much.  (4)  Have  the 
mask  made.  (5)  Expose  and  etch  the  slice.  (6)  Cut  up  the  slice  into 
chips.  (7)  Mount  the  chips.  (8)  Test  the  sample. 

This  basic  description  of  digital  logic  and  the  CMOS  array  provide 
the  basic  building  block  for  designing  custom  digital  LSI's,  using  an 
array  of  gates.  A design  engineer  can  mcdce  the  initial  layout  of  the 
circuit.  He  c^u^  assess  how  changes  in  logic  will  affect  the  custom 
layout.  And,  in  general,  he  cem  assess  the  degree  of  circuit  ccnplexity 
that  can  be  accommodated  by  custom  digital  LSI’s. 


LITERATURE  CITED 

(1)  S.  S.  Eaton,  Timekeeping  Revolution  through  COS/MOS  Technology,  RCA 
COS/MOS  Technology  (1973),  33-41. 

(2)  D.  K.  Morgan,  COS/MOS  Integrated  Circuits  in  the  Automobile 
Environment,  RCA  COS/MOS  Technology  (1973),  45-51. 

(3)  R.  A.  Bishop  and  D.  R.  Carley,  Fundamentals  of  COS/MOS  Integrated 
Circuits,  RCA  COS/MOS  Technology  (1973),  8-11. 

(4)  A.  B.  Marcovitz  and  J.  H.  Pugsley,  Introduction  to  Switching  System 
Design,  John  Wiley  and  Sons,  New  York  (1971). 

(5)  J.  T.  Doyle  and  C.  A.  Neugebauer,  Approaches  to  Custom  Large  Scale 
Integration,  General  Electric  Company,  Schenectady , NY , AFAL-TR-73-66 
(March  1973) . 


(6)  R.  O.  Berg  et  al.  Approaches  to  Custom  LSI,  Honeywell,  Inc., 
AFAL-TR-73-16  (April  1973) . 


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